The emergence of co-packaged optical modules (CPOs) is gradually changing the way data centres and high-performance networks operate. They address several unavoidable challenges: bandwidth density, energy consumption and future scalability. CPOs enhance interconnect bandwidth and energy efficiency by packaging optical and electronic components together directly, while also shortening electrical link lengths. This design is becoming increasingly important as data centre traffic surges, especially in light of the ever-growing demands of artificial intelligence and high-performance computing.
Compared to traditional pluggable optical modules, CPO demonstrates greater advantages at high data rates. Previously, increasing module speed inevitably led to higher power consumption. The CPO solution, however, reduces power draw—early tests indicate reductions of 30% to 50%. Combined with advancements in chip-on-package (CoP) technology and 3D-IC packaging, the integration of optical components with silicon wafers has become tighter, significantly reducing signal attenuation and energy loss.
As data rates surpass 800G and even 1.6T thresholds, CPO provides a clear evolution path for future networks. With increasing participation from manufacturers and institutions—particularly deepening exploration in AI applications—CPO is widely anticipated to achieve breakthroughs in both efficiency and capacity, thereby driving substantial transformation in network infrastructure.
Co-packaged optical (CPO) modules take an integrated approach by bundling disparate components together. By placing optical modules and silicon chips on a single substrate, CPO modules address the challenges of bandwidth, power consumption, and cost in next-generation networks directly. CPO technology combines fiber optics, digital signal processing (DSP), application-specific integrated circuit (ASIC) design, and advanced packaging and testing processes. CPO provides tangible benefits for expanding data centers in both horizontal and vertical directions.
Traditional pluggable optical modules often use high-power digital signal processors (DSPs) to make up for losses during signal transmission from the application-specific integrated circuit (ASIC). As SerDes technology advances to 212 Gbps PAM-4 and beyond, these losses intensify, creating a greater dependence on DSPs. While Linear Regenerative Optical (LRO) or Linear Pluggable Optical (LPO) modules attempt to eliminate DSPs, they remain susceptible to interconnect losses. In contrast, Co-Packaged Optical (CPO) modules integrate the optical module directly onto the same substrate interface as the ASIC. This achieves higher integration, minimizes transmission path losses, and maintains power consumption within a more optimal range.
In terms of power consumption, CPO performance has been validated by multiple manufacturers. Early solutions from Broadcom and Cisco showed power savings of 30% to 50%, achieving interconnect energy efficiency below one pJ/bit. Ayar Labs took this further, achieving a throughput of 16 Tbps in both directions while using less than five pJ/bit. Here are some key ways to save energy:
Lossless Copper Cabling
Traditional pluggable optical modules require signals to travel from ASIC chips through copper links to the front panel—a lengthy, energy-intensive process. CPO designs mount the active components and optical transceivers on the same substrate, eliminating all losses and distortion caused by copper traces on the motherboard.
Reduced Reliance on DSPs
In architectures with more than 25G/channel, DSP retimers are almost essential in pluggable optical modules to compensate for signal loss and distortion. However, DSPs themselves increase system power consumption by 25% to 30%. CPO integrates chips and optical components, significantly reducing copper wiring losses. This allows designers to use less DSP, saving power and money.
Laser Integration Methods
There are two approaches for laser placement. The common method uses an external laser, feeding light into the CPO via fiber, but this often incurs 30% to 50% optical power loss. The alternative integrates the laser directly onto the chip. If thermal management and reliability are assured, this design offers superior coupling efficiency.
High Bandwidth and Low Latency
CPOs also deliver significant advantages in bandwidth and latency. Eliminating redundant DSPs and long copper traces enables more direct, cleaner signal transmission. Delays introduced by additional components like DSPs and copper trace parasitics are virtually absent in CPO architectures.
CPO in Network Applications
CPO is currently deployed primarily in front-end networks of data centers to connect servers. Its high bandwidth, low latency, and energy efficiency make it one of the most promising solutions in next-generation optical Ethernet technology, particularly suited for network-level applications.
800G OSFP vs. 800G CPO
OIO and High-Performance Computing for AI/ML
The industry is exploring new architectures due to the computational demands of artificial intelligence and machine learning. OIO-powered AI backend networks. This is seen as a key direction for supporting future computing clusters.
Traditional HPC systems suffer from rigid resource allocation rules that constrain data transfer, preventing full performance utilization. While CPU and GPU speeds have increased, I/O infrastructure has not kept pace. This results in delayed data transmission, idle computing units, and diminished overall efficiency.
As AI/ML tasks grow increasingly large-scale, this contradiction intensifies. The solution lies in a network architecture capable of delivering high-speed, low-latency, lossless transmission with scalability—precisely the context in which OIO emerged. It carries high expectations to revolutionize existing performance bottlenecks, potentially.
The Transformation of HPC Architecture
In the world of high-performance computing, decomposable architectures are slowly replacing the old isolated models. The new approach involves separating memory, computing, and storage parts of a computer, and then putting them together in flexible groups through advanced OIO connections. This makes it so that you can easily adjust how you use your resources, which is better than the old way of doing things because it's more flexible and efficient.
Supplier Lock-in Issues
When both switches and optical components come from the same vendor, operators face limited choices. Once significant investment is made in a particular ecosystem, switching to other suppliers' products becomes difficult. This reduces flexibility for component upgrades or replacements and can lead to dependency over the long term.
Maintenance and Reliability
Pluggable optical modules are great because they're highly modular. This means that if a part breaks, it can be easily replaced. They're also interchangeable with products from any manufacturer. But this isn't the case for CPOs. When an optical component stops working, the entire switch often needs to be disassembled. This makes replacing it much more difficult and expensive. To address this, some designs incorporate high-risk components, such as lasers, in parts that can be replaced remotely. Others explore pluggable optical connectors to facilitate easier maintenance.
Thermal Challenges
Putting photonic chips inside electronic packages can increase the risk of thermal interference. Heaters and laser sources in the photonic chip generate heat, while thermal energy from electronic chips flows to the photonic section. Combined with the system-level cooling design, thermal behavior becomes significantly more complex. Therefore, a comprehensive thermal analysis is required from the chip level to the system level.
Signal and Power Integrity
CPO systems necessitate global transient simulation to ensure both stable signal transmission and uninterrupted power supply. This involves accounting for coupling between electrical and photonic circuits, while also incorporating parasitic effects introduced by various electrical interconnects during the packaging stage.
Scalability and Edge Bandwidth Density
A key metric for CPO and OIO is edge bandwidth density—how many fibers can be accommodated at the chip's periphery. Fibers are usually edge-coupled. The different size between the fiber and the waveguide creates problems when it comes to fan-out. Try to imagine placing thousands of fibers onto a substrate without increasing its size—this almost always hits a wall. To overcome this, the industry has proposed methods such as V-groove structures, which arrange fibers vertically to prevent damage when they are connected. New approaches, such as grating-based microlenses, are also under active research.
Manufacturing and Testing Challenges
Achieving actual mass production hinges on cost and yield rates. Ensuring consistent quality and robust testing processes is particularly critical in multi-vendor supply chain scenarios. As demand grows and capital investment increases, these requirements will continue to escalate.
In the semiconductor industry, a currently popular approach involves using chiplet designs, which differ from integrating all functions into a single system-on-chip (SoC). The chiplet approach breaks down functionality into multiple independent small chips, each of which can be packaged and combined to work together. This design offers greater flexibility in chip design and simplifies the transition from traditional SoCs to system-in-package (SiP) architectures. Chiplet technology may prove to be a key driver in advancing the adoption of CPO technology. They enable the combination of different technologies within the same package—for example, pairing an optical I/O chiplet built on a mature CMOS node with an ASIC manufactured on a cutting-edge process. That mix lowers cost, improves yield, and makes the whole ecosystem more adaptable.
At the same time, 3D-IC technology is opening up new possibilities for integration density. Current CPO designs typically place optical and electrical chips side by side on a low-loss substrate; however, stacking them vertically is the next logical step. A 3D-IC CPO architecture would enable the integration of OIO and ASIC components in three dimensions, offering ultra-low power and extremely high bandwidth chip-to-chip links. This kind of packaging enables bigger, more complex designs, but it also introduces new challenges. Engineers increasingly need multi-physics and electromagnetic simulations to capture emerging effects that weren’t a concern at more minor scales.
Meanwhile, pluggable optics are not going away anytime soon. Linear-drive pluggable optics (LPO) are evolving alongside CPO, sharing the same idea of removing the DSP to cut power consumption. While CPO shrinks optics and electronics into an incredibly compact footprint, pluggables are also undergoing miniaturization to address their historically bulky form factor. The two approaches may ultimately complement each other rather than compete directly, especially as data centers seek flexible deployment options.
Still, for CPO to move beyond the proof-of-concept stage and gain broad market trust, several conditions must be met. The industry will need to demonstrate a robust multi-vendor business model, accompanied by tangible cost and power reductions. Just as important is the creation of missing pieces, such as standardized optical interfaces and reusable IP blocks. No single company can pull this off alone. Progress depends on collaboration across the supply chain—EDA vendors, chip designers, system architects, packaging houses, test equipment providers, and foundries all have to work in sync. Building that ecosystem is no small task, but the pressure is mounting. With AI and machine learning workloads pushing network and compute demands into uncharted territory, the race has already begun.
